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LTC4365 1 4365f typical application features description uv, ov and reverse supply protection controller 12v automotive application applications n wide operating voltage range: 2.5v to 34v n overvoltage protection to 60v n reverse supply protection to C40v n blocks 50hz and 60hz ac power n no input capacitor or tvs required for most applications n adjustable undervoltage and overvoltage protection range n charge pump enhances external n-channel mosfet n low operating current: 125a n low shutdown current: 10a n fault status output n compact 8-lead, 3mm 2mm dfn and tsot-23 (thinsot?) packages n portable instrumentation n industrial automation n laptops n automotive l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot, no r sense and hot swap are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. v in uv ov shdn ov = 18v uv = 3.5v 4365 ta01a v out fault gate v in 12v v out 3a si4946 gnd LTC4365 510k 1820k 243k 59k load protected from reverse and overvoltage at v in the ltc ? 4365 protects applications where power supply input voltages may be too high, too low or even negative. it does this by controlling the gate voltages of a pair of external n-channel mosfets to ensure that the output stays within a safe operating range. the LTC4365 can withstand voltages between C40v and 60v and has an operating range of 2.5v to 34v, while consuming only 125a in normal operation. two comparator inputs allow configuration of the overvoltage (ov) and undervoltage (uv) set points using an external resistive divider. a shutdown pin provides external control for enabling and disabling the mosfets as well as placing the device in a low current shutdown state. a fault output provides status of the gate pin pulling low. a fault is indicated when the part is in shutdown or the input voltage is outside the uv and ov set points. ?30v gnd 10v/div 30v 4365 ta01b 1s/div uv = 3.5v ov = 18v v out v out v in v in valid window www.datasheet.in
LTC4365 2 4365f pin configuration absolute maximum ratings supply voltage (note 1) v in .......................................................... C40v to 60v input voltages (note 3) uv, shdn .............................................. C0.3v to 60v ov ............................................................ C0.3v to 6v v out ....................................................... C0.3v to 40v output voltages (note 4) fa u lt ..................................................... C0.3v to 60v gate ....................................................... C40v to 45v top view 9 gnd ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1 gnd ov uv v in shdn fault v out gate t jmax = 150c, ja = 76c/w exposed pad (pin 9) pcb ground connection optional 1 2 3 4 8 7 6 5 top view ts8 package 8-lead plastic tsot-23 gate v out fault shdn v in uv ov gnd t jmax = 150c, ja = 195c/w order information l f f tape and reel mini tape and reel part marking package description temperature range LTC4365cddb#trmpbf LTC4365cddb#trpbf lfks 8-lead (3mm 2mm) plastic dfn 0c to 70c LTC4365iddb#trmpbf LTC4365iddb#trpbf lfks 8-lead (3mm 2mm) plastic dfn C40c to 85c LTC4365hddb#trmpbf LTC4365hddb#trpbf lfks 8-lead (3mm 2mm) plastic dfn C40c to 125c LTC4365cts8#trmpbf LTC4365cts8#trpbf ltfkt 8-lead plastic tsot-23 0c to 70c LTC4365its8#trmpbf LTC4365its8#trpbf ltfkt 8-lead plastic tsot-23 C40c to 85c LTC4365hts8#trmpbf LTC4365hts8#trpbf ltfkt 8-lead plastic tsot-23 C40c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating ambient temperature range LTC4365c ................................................ 0c to 70c LTC4365i ............................................. C40c to 85c LTC4365h .......................................... C40c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) for tsot only ................................................... 300c www.datasheet.in
LTC4365 3 4365f electrical characteristics symbol parameter conditions min typ max units v in , v out v in input voltage range operating range protection range l l 2.5 C40 34 60 v v i vin input supply current shdn = 0v, v in = v out , C40c to 85c shdn = 0v, v in = v out , C40c to 125c shdn = 2.5v l l l 10 10 25 50 100 150 a a a i vin(r) reverse input supply current v in = C40v, v out = 0v l C1.2 C1.8 ma v in(uvlo) input supply undervoltage lockout v in rising l 1.8 2.2 2.4 v i vout v out input current shdn = 0v, v in = v out shdn = 2.5v, v in = v out v in = C40v, v out = 0v l l l 6 100 20 30 250 50 a a a gate v gate n-channel gate drive (gate-v out ) v in = v out = 5.0v, i gate = C1a v in = v out = 12v to 34v, i gate = C1a l l 3 7.4 3.6 8.4 4.2 9.8 v v i gate(up) n-channel gate pull up current gate = v in = v out = 12v l C12 C20 C30 a i gate(fast) n-channel gate fast pull down current fast shutdown, gate = 20v, v in = v out = 12v l 31 50 72 ma i gate(slow) n-channel gate gentle pull down current gentle shutdown, gate = 20v, v in = v out = 12v l 50 90 150 a t gate(fast) n-channel gate fast turn off delay c gate = 2.2nf, uv or ov fault l 2 4 s t gate(slow) n-channel gentle turn off delay c gate = 2.2nf, shdn falling, v in = v out = 12v l 150 250 350 s t recovery gate recovery delay time v in = 12v, power good to d v gate > 0v l 26 36 49 ms uv, ov v uv uv input threshold voltage uv falling v gate = 0v l 492.5 500 5 07. 5 mv v ov ov input threshold voltage ov rising v gate = 0v l 492.5 500 5 07. 5 mv v uvhyst uv input hysteresis l 20 25 32 mv v ovhyst ov input hysteresis l 20 25 32 mv i leak uv, ov leakage current v = 0.5v, v in = 34v l 10 na t fault uv, ov fault propagation delay overdrive = 50mv v in = v out = 12v l 1 2 s shdn v shdn shdn input threshold shdn falling to v gate = 0v l 0.4 0.75 1.2 v i shdn shdn input current shdn = 0.75v, v in = 34v l 10 na t start delay coming out of shutdown mode shdn rising to v gate > 0v, v in = v out = 12v l 400 800 1200 s t shdn(f) shdn to fa u lt asserted v in = v out = 12v l 1.5 3 s t lowpwr delay from turn off to low power operation v in = v out = 12v l 26 36 55 ms fau lt v ol fa u lt output voltage low i fault = 500a l 0.15 0.4 v i fault fa u lt leakage current fa u lt = 5v, v in = 34v l 20 na the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 2.5v to 34v, unless otherwise noted. (note 2) note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3. these pins can be tied to voltages below C0.3v through a resistor that limits the current below 1ma. note 4. the gate pin is referenced to v out and does not exceed 44v for the entire operating range. www.datasheet.in
LTC4365 4 4365f typical performance characteristics v out operating current vs temperature v out shutdown current vs temperature v out current vs reverse v in v in operating current vs temperature v in shutdown current vs v in v in current vs v in (C40 to 60v) gate current vs gate drive gate drive vs v in gate drive vs temperature temperature (c) ?50 0 i vin (a) 20 40 60 80 0 50 100 4365 g01 100 ?25 25 75 125 shdn = 2.5v v in = 12v v in = 34v v out = v in v in = 2.5v v in (v) 0 0 i vin (a) 5 10 15 25 20 10 20 35 30 4365 g02 30 5 15 25 v in = v out shdn = 0v 25c ?45c 125c 70c v in (v) ?50 ?1600 i vin (a) ?1200 ?800 ?400 0 0 50 75 4365 g03 400 ?25 25 shdn = uv = 0v 25c 25c ?45c 125c temperature (c) ?50 0 i vout (a) 40 80 120 160 0 100 75 125 4365 g04 200 ?25 25 50 shdn = 2.5v v out = 34v v out = 12v v out = 2.5v v in = v out temperature (c) ?50 0 i vout (a) 5 10 15 0 25 75 100 125 4365 g05 20 ?25 50 shdn = 0v v out = 34v v out = 12v v out = 2.5v v in = v out v in (v) 0 i vout (a) 5 10 15 20 0 ?10 ?30 ?40 ?50 4365 g06 25 ?20 ?45c 25c 125c v out = 0v v in (v) 0 ?v gate (v) 2 4 6 8 10 0 5 15 20 35 25 30 4365 g07 12 10 v out = 0v v out = v in t = 25c i gate = ?1a temperature (c) ?50 0 ?v gate (v) 2 4 6 8 0 50 100 4365 g08 10 ?25 25 75 125 v in = v out = 12v v in = v out = 34v i gate = ?1a v in = v out = 2.5v ?v gate (v) 0 0 i gate(up) (a) 5 10 15 20 2 6 10 4365 g09 25 4 8 v in = v out = 12v 125c 25c ?45c www.datasheet.in
LTC4365 5 4365f uv/ov propagation delay vs overdrive recovery delay time vs temperature recovery delay time vs v in ov threshold vs temperature uv/ov leakage vs temperature uv threshold vs temperature typical performance characteristics temperature (c) ?50 492.5 v uv (mv) 495.0 497.5 500.0 502.5 505.0 0 50 100 4365 g10 507.5 ?25 25 75 125 v in = v out = 12v temperature (c) ?50 492.5 v ov (mv) 495.0 497.5 500.0 502.5 505.0 0 50 100 4365 g11 507.5 ?25 25 75 125 v in = v out = 12v temperature (c) ?75 0 i leak (na) 0.25 0.50 0.75 4365 g12 1.00 ?25 25 75 175 125 v uv/ov = 0.5v v in = 12v uv ov overdrive (mv) 1 0 t fault (s) 8 4 12 16 4365 g13 20 10 100 1000 v in = v out = 12v t = 25c temperature (c) ?50 0 t recovery (ms) 10 20 30 40 50 0 50 100 4365 g14 ?25 25 75 125 v in = 34v v in = 12v v in = 2.5v v in (v) 0 0 t recovery (ms) 10 20 30 40 50 10 20 35 4365 g15 5 15 30 25 125c 25c ?45c 4365 g16 2.5ms/div gate v out v in 10f, 1k load on v out 60v dual nch mosfet 1v/div 20v/div gnd gnd 4365 g17 250s/div v out gate 100f, 12 load on v out 60v si9945 dual nch mosfet v in = 12v shdn 5v/div 3v/div gnd gnd 4365 g18 250s/div v out shdn gate 100f, 12 load on v out 60v si9945 dual nch mosfet 5v/div 3v/div gnd gnd ac blocking turn-on timing turn-off timing www.datasheet.in
LTC4365 6 4365f pin functions exposed pad: connect to device ground. fau lt : fault indication output. this high voltage open drain output is pulled low if uv is below its monitor threshold, if ov is above its monitor threshold, if shdn is low, or if v in has not risen above v in(uvlo) . gate: gate drive output for external n-channel mosfets. an internal charge pump provides 20a of pull-up current and up to 9.8v of enhancement to the gate of an external n-channel mosfet. when turned off, gate is pulled just below the lower of v in or v out . when v in goes negative, gate is automati - cally connected to v in . gnd: device ground. ov: overvoltage comparator input. connect this pin to an external resistive divider to set the desired v in overvoltage fault threshold. input to an accurate, fast (1s) compara - tor with a 0.5v rising threshold and 25mv of hysteresis. when ov rises above its threshold, a 50ma current sink pulls down on the gate output. when ov falls back below 0.475v, and after a 36ms recovery delay waiting period, the gate charge pump is enabled. the low leakage current of the ov input allows the use of large valued resistors for the external resistive divider. connect to gnd if unused. shdn : shutdown control input. shdn high enables the gate charge pump which in turn enhances the gate of an external n-channel mosfet. a low on shdn generates a pull down on the gate output with a 90a current sink and places the LTC4365 in low current mode (10a). if unused, connect to v in . if v in goes below ground, or if v in rings to 60v, use a current limiting resistor of at least 100k. uv: undervoltage comparator input. connect this pin to an external resistive divider to set the desired v in undervoltage fault threshold. input to an accurate, fast (1s) comparator with a 0.5v falling threshold and 25mv of hysteresis. when uv falls below its threshold, a 50ma current sink pulls down on the gate output. when uv rises back above 0.525v, and after a 36ms recovery delay waiting period, the gate charge pump is enabled. the low leakage current of the uv input allows the use of large valued resistors for the external resistive divider. if unused, connect to v in . while connected to v in , if v in goes below ground, or if v in rings to 60v, use a current limiting resistor of at least 100k. v in : power supply input. maximum protection range: C40v to 60v. operating range: 2.5v to 34v. v out : output voltage sense input. this pin senses the volt - age at the output side of the external n-channel mosfet. the gate charge pump voltage is referenced to v out . it is used as the charge pump input when v out is greater than approximately 6.5v. www.datasheet.in
LTC4365 7 4365f block diagram v in ?40v to 60v 5v internal supply 6.5v internal supply ldo 2.2v uvlo 0.5v gnd 25mv hysteresis 4365 bd i gate reverse protection closes switch when v in is negative enable gate pulldown fault off turn off 50ma 90a shdn shdn gate charge pump f = 400khz v out uv ov ? + delay timers logic ? + ? + fault gate www.datasheet.in
LTC4365 8 4365f operation many of todays electronic systems get their power from external sources such as a wall wart adapter, batteries and custom power supplies. these power sources are often unreliable, wired incorrectly, out of spec, or just plain wrong. this can lead to supply voltages that are too high, too low, or even negative. if these power sources are applied directly to the electronic systems, the systems could be subject to damage. the LTC4365 is an input voltage fault protection n-channel mosfet controller. the part isolates an input supply from its load to protect the load from unexpected supply voltage conditions, while providing a low loss path for qualified power. to protect electronic systems from improperly connected power supplies, system designers will often add discrete diodes, transistors and high voltage comparators. the high voltage comparators enable system power only if the input supply falls within a desired voltage window. a schottky diode or p-channel mosfet typically added in series with the supply protects against reverse supply connections. the LTC4365 provides accurate overvoltage and undervoltage comparators to ensure that power is ap - plied to the system only if the input supply meets the user selectable voltage window. reverse supply protection circuits automatically isolate the load from negative input voltages. during normal operation, a high voltage charge pump enhances the gate of external n-channel power mosfets. power consumption is 10a during shutdown and 125a while operating. the LTC4365 integrates all these functions in tiny tsot-23 and 3mm 2mm dfn packages. applications information the LTC4365 is an n-channel mosfet controller that protects a load from faulty supply connections. a basic application circuit using the LTC4365 is shown in figure 1. the circuit provides a low loss connection from v in to v out as long as the voltage at v in is between 3.5v and v in uv ov shdn ov = 18v uv = 3.5v 4365 f01 v out fault gate v in 12v nominal v out 3.5v to 18v si4946 60v dual gnd LTC4365 r5 100k c out 100f r3 1820k r2 243k r1 59k + m1 m2 figure 1. LTC4365 protects load from C40v to 60v v in faults 18v. voltages at v in outside of the 3.5v to 18v range are prevented from getting to the load and can be as high as 60v and as low as C40v. the circuit of figure 1 protects against negative voltages at v in as shown. no other ex - ternal components are needed. during normal operation, the LTC4365 provides up to 9.8v of gate enhancement to the external back-to-back n-channel mosfets. this turns on the mosfet, thus connecting the load at v out to the supply at v in . gate drive the LTC4365 turns on the external n-channel mosfets by driving the gate pin above v out . the voltage differ - ence between the gate and v out pins (gate drive) is a function of v in and v out . www.datasheet.in
LTC4365 9 4365f overvoltage and undervoltage protection the LTC4365 provides two accurate comparators to moni - tor for overvoltage (ov) and undervoltage (uv) conditions at v in . if the input supply rises above the user adjustable ov threshold, the gate of the external mosfet is quickly turned off, thus disconnecting the load from the input. similarly, if the input supply falls below the user adjust - able uv threshold, the gate of the external mosfet also is quickly turned off. figure 3 shows a uv/ov application for an input supply of 12v. figure 2. gate drive (gate C v out ) vs v out applications information figure 2 highlights the dependence of the gate drive on v in and v out . when system power is first turned on ( shdn low to high, v out = 0v), gate drive is at a maximum for all values of v in . this helps prevent start-up problems into heavy loads by ensuring that there is enough gate drive to support the load. as v out ramps up from 0v, the absolute value of the gate voltage remains fixed until v out is greater than the lower of (v in C1v) or 6v. once v out crosses this threshold, gate drive begins to increase up to a maximum of 9.8v (for v in 12v). the curves of figure 2 were taken with a gate load of C1a. if there were no load on gate, the gate drive for each v in would be slightly higher. note that when v in is at the lower end of the operating range, the external n-channel mosfet must be selected with a corresponding lower threshold voltage. v in 12v uv th = 3.5v ov th = 18v 4365 f03 discharge gate with 50ma sink LTC4365 ov comparator uv comparator r3 1820k uv 0.5v 0.5v ov r2 243k r1 59k ? + 25mv ? + 25mv figure 3. uv, ov comparators monitor 12v supply the external resistive divider allows the user to select an input supply range that is compatible with the load at v out . furthermore, the uv and ov inputs have very low leakage currents (typically < 1na at 100c), allowing for large values in the external resistive divider. in the applica - tion of figure 3, the load is connected to the supply only if v in lies between 3.5v and 18v. in the event that v in goes above 18v or below 3.5v, the gate of the external n-channel mosfet is immediately discharged with a 50ma current sink, thus isolating the load from the supply. table 1 lists some external mosfets compatible with different v in supply voltages. table 1. dual mosfets for various supply ranges v in mosfet v th(max) v gs(max) v ds(max) 2.5v sib914 0.8v 5v 8v 3.3v si5920 1.0v 5v 8v 5v si7940 1.5v 8v 12v 30v si4230 3.0v 20v 30v 60v si9945 3.0v 20v 60v v out (v) 0 0 ?v gate (v) 2 4 6 10 8 12 9 15 4365 f02 3 6 12 v in = 30v v in = 12v v in = 5v v in = 3.3v v in = 2.5v t = 25c i gate = ?1a www.datasheet.in
LTC4365 10 4365f figure 4 shows the timing associated with the uv pin. once a uv fault propagates through the uv comparator (t fault ), the fa u lt output is asserted low and a 50ma current sink discharges the gate pin. as v out falls, the gate pin tracks v out . applications information figure 5 shows the timing associated with the ov pin. once an ov fault propagates through the ov comparator (t fault ), the fa u lt output is asserted low and a 50ma current sink discharges the gate pin. as v out falls, the gate pin tracks v out . procedure for selecting uv/ov external resistor values the following 3-step procedure helps select the resistor values for the resistive divider of figure 3. this procedure minimizes uv and ov offset errors caused by leakage currents at the respective pins. 1. choose maximum tolerable offset at the uv pin, v os(uv) . divide by the worst case leakage current at the uv pin, i uv (10na). set the sum of r1 + r2 equal to v os(uv) divided by 10na. note that due to the presence of r3, the actual offset at uv will be slightly lower: r 1+ r 2 = v o s ( u v ) i u v 2. select the desired v in uv trip threshold, uv th . find the value of r3: r 3 = 2 ? v o s ( u v ) i u v ? u v t h ? 0.5 v ( ) 3. select the desired v in ov trip threshold, ov th . find the values of r1 and r2: r 1 = v o s ( u v ) i u v + r 3 2 ? o v t h r 2 = v o s ( u v ) i u v ? r 1 the example of figure 3 uses standard 1% resistor values. the following parameters were selected: v os(uv) = 3mv i uv = 10na uv th = 3.5v ov th = 18v 4365 f04 fault gate t fault t gate(fast) v uv v uv + v uvhyst t fault t recovery external n-channel mosfet turns off uv 4365 f05 fault gate t fault t gate(fast) v ov v ov ? v ovhyst t fault t recovery external n-channel mosfet turns off ov figure 4. uv timing (ov < (v ov C v ovhyst ), shdn > 1.2v) figure 5. ov timing (uv > (v uv + v uvhyst ), shdn > 1.2v) when both the uv and ov faults are removed, the external mosfet is not immediately turned on. the input supply must remain within the user selected power good window for at least 36ms (t recovery ) before the load is again connected to the supply. this recovery timeout period filters noise (including line noise) at the input supply and prevents chattering of power at the load. www.datasheet.in
LTC4365 11 4365f applications information the resistor values can then be solved: 1. r 1 + r 2 = 3 m v 10 na = 300 k 2. r 3 = 2 ? 3 m v 10 na ? ( 3.5 v ? 0.5 v ) = 1.8 m the closest 1% value: r3 = 1.82m: 3. r 1 = 300 k + 1.82 m 2 ? 18 v = 58. 9 k the closest 1% value: r1 = 59k: r2 = 300k C 59k = 241k the closest 1% value: r2 = 243k therefore: ov = 17.93v, uv = 3.51v. reverse v in protection the LTC4365s rugged and hot-swappable v in input helps protect the more sensitive circuits at the output load. if the input supply is plugged in backwards, or a negative supply is inadvertently connected, the LTC4365 prevents this negative voltage from passing to the output load. the LTC4365 employs a novel, high speed reverse sup - ply voltage monitor. when the negative v in voltage is detected, an internal switch connects the gates of the external back-to-back n-channel mosfets to the nega - tive input supply. as shown in figure 6, external back-to-back n-channel mosfets are required for reverse supply protection. when v in goes negative, the reverse v in comparator closes the internal switch, which in turn connects the gates of the external mosfets to the negative v in voltage. the body diode (d1) of m1 turns on, but the body diode (d2) of m2 remains in reverse blocking mode. this means that the common source connection of m1 and m2 remains about a diode drop higher than v in . since the gate voltage of m2 is shorted to v in , m2 will be turned off and no cur - rent can flow from v in to the load at v out . note that the voltage rating of m2 must withstand the reverse voltage excursion at v in . figure 7 illustrates the waveforms that result when v in is hot plugged to C20v. v in , gate and v out start out at ground just before the connection is made. due to the parasitic inductance of the v in and gate connections, the voltage at the v in and gate pins ring significantly below C20v. therefore, a 40v n-channel mosfet was selected to survive the overshoot. the speed of the LTC4365 reverse protection circuits is evident by how closely the gate pin follows v in during the negative transients. the two waveforms are almost indistinguishable on the scale shown. figure 6. reverse v in protection circuits v in 4365 f06 v out gate v in = ?40v reverse v in comparator closes switch when v in is negative gnd LTC4365 m1 d1 d2 m2 + ? + to load c out figure 7. hot swapping v in to C20v ?20v 5v/div gnd 4365 f07 500ns/div gate v out v in www.datasheet.in
LTC4365 12 4365f the trace at v out , on the other hand, does not respond to the negative voltage at v in , demonstrating the desired reverse supply protection. the waveforms of figure 7 were captured using a 40v dual n-channel mosfet, a 10f ceramic output capacitor and no load current on v out . recovery timer the LTC4365 has a recovery delay timer that filters noise at v in and helps prevent chatter at v out . after either an ov or uv fault has occurred, the input supply must return to the desired operating voltage window for at least 36ms in order to turn the external mosfet back on as illustrated in figures 4 and 5. going out of and then back into fault in less than 36ms will keep the mosfet off continuously. similarly, coming out of shutdown ( shdn low to high) triggers an 800s start-up delay timer (see figure 10). the recovery timer is also active while the LTC4365 is powering up. the 36ms timer starts once v in rises above v in(uvlo) and v in lies within the user selectable uv/ov power good window. see figure 8. gentle shutdown the shdn input turns off the external mosfets in a gentle, controlled manner. when shdn is asserted low, a 90a current sink slowly begins to turn off the external mosfets. once the voltage at the gate pin falls below the voltage at the v out pin, the current sink is throttled back and a feedback loop takes over. this loop forces the gate voltage to track v out , thus keeping the external mosfets off as v out decays. note that when v out < 4.5v, the gate pin is pulled to within 400mv of ground. gentle gate turn off reduces load current slew rates and mitigates voltage spikes due to parasitic inductances. to further decrease gate pin slew rate, place a capaci - tor across the gate and source terminals of the external mosfets. the waveforms of figure 9 were captured using the si4230 dual n-channel mosfets, and a 2a load with 100f output capacitor. applications information 4365 f08 gate mosfet off mosfet on v in v in(uvlo) t recovery figure 8. recovery timing during power-on (ov = gnd, uv = shdn = v in ) figure 9. gentle shutdown: gate tracks v out as v out decays gate v out t gate(slow) gate = v out t start t shdn(f) v gate shdn 4365 f10 fault figure 10. gentle shutdown timing fault status the fa u lt high voltage open drain output is driven low if shdn is asserted low, if v in is outside the desired uv/ov voltage window, or if v in has not risen above v in(uvlo) . figures 4, 5 and 10 show the fa u lt output timing. 5v/div 4365 f9 100s/div gate v out shdn v in = 12v t = 25c gnd www.datasheet.in
LTC4365 13 4365f select between two input supplies with the part in shutdown, the v in and v out pins can be driven by separate power supplies. the LTC4365 then automatically drives the gate pin just below the lower of the two supplies, thus turning off the external back-to-back mosfets. the application of figure 11 uses two LTC4365s to select between two power supplies. care should be taken to ensure that only one of the two LTC4365s is enabled at any given time. applications information figure 11. selecting one of two supplies v in v2 shdn 4365 f11 v out gate LTC4365 v in v1 sel 0 1 out v1 v2 out m2 m1 m2 m1 sel shdn v out gate LTC4365 limiting inrush current during turn-on the LTC4365 turns on the external n-channel mosfet with a 20a current source. the maximum slew rate at the gate pin can be reduced by adding a capacitor on the gate pin: s l e w r a t e = 20 a c g a t e since the mosfet acts like a source follower, the slew rate at v out equals the slew rate at gate. therefore, inrush current is given by: i i n r u s h = c o u t c g a t e ? 20 a for example, a 1a inrush current to a 330f output capacitance requires a gate capacitance of: c g a t e = 20 a ? c o u t i i n r u s h c g a t e = 20 a ? 330 f 1 a = 6.6 nf the 6.8nf c gate capacitor in the application circuit of figure 13 limits the inrush current to approximately 1a. r gate makes sure that c gate does not affect the fast gate turn off characteristics during uv/ov faults, or during reverse v in connection. r4a and r4b help prevent high frequency oscillations with the external n-channel mosfet and related board parasitics. v in uv ov shdn ov = 30v 4365 f12 v out fault gate v in 24v si7120dn 60v v out gnd LTC4365 r2 2370k r1 40.2k c out 100f + figure 12. small footprint single mosfet application protects against 60v single mosfet application when reverse v in protection is not needed, only a single external n-channel mosfet is necessary. the applica - tion circuit of figure 12 connects the load to v in when v in is less than 30v, and uses the minimal set of external components. 4365 f13 v in v in v out r4b 10 r4a 10 c out 330f v out gate LTC4365 r gate 5.1k c gate 6.8nf + m2 m1 figure 13. limiting inrush current with c gate www.datasheet.in
LTC4365 14 4365f applications information transients during ov fault the circuit of figure 14 was used to display transients during an overvoltage condition. the nominal input supply is 24v and it has an overvoltage threshold of 30v. the parasitic inductance is that of a 1 foot wire (roughly 300nh). figure 15 shows the waveforms during an overvoltage condition at v in . these transients depend on the parasitic inductance and resistance of the wire along with the ca - pacitance at the v in node. d1 is an optional power clamp (tvs, tranzorb) recommended for applications where the dc input voltage can exceed 24v and with large v in parasitic inductance. no clamp was used to capture the waveforms of figure 15. in order to maintain reverse supply protection, d1 must be a bi-directional clamp rated for at least 225w peak pulse power dissipation. mosfet selection to protect against a negative voltage at v in , the external n-channel mosfets must be configured in a back-to- back arrangement. dual n-channel packages are thus the best choice. the mosfet is selected based on its power handling capability, drain and gate breakdown voltages, and threshold voltage. the drain to source breakdown voltage must be higher than the maximum voltage expected between v in and v out . note that if an application generates high energy transients during normal operation or during hot swap?, the external mosfet must be able to withstand this transient voltage. due to the high impedance nature of the charge pump that drives the gate pin, the total leakage on the gate pin must be kept low. the gate drive curves of figure 2 were measured with a 1a load on the gate pin. therefore, the leakage on the gate pin must be no greater than 1a in order to match the curves of figure 2. higher leakage currents will result in lower gate drive. the dual n-channel mosfets shown in table 1 all have a maximum gate leakage cur - rent of 100na. additionally, table 1 lists representative mosfets that would work at different values of v in . layout considerations the trace length between the v in pin and the drain of the external mosfet should be minimized, as well as the trace length between the gate pin of the LTC4365 and the gates of the external mosfets. place the bypass capacitors at v out as close as possible to the external mosfet. use high frequency ceramic capacitors in addition to bulk capacitors to mitigate hot swap ringing. place the high frequency capacitors closest to the mosfet. note that bulk capacitors mitigate ringing by virtue of their esr. ceramic capacitors have low esr and can thus ring near their resonant frequency. v in uv ov shdn ov = 30v 4365 f14 v out fault gate m1 m2 v in 24v si9945 60v 12 inch wire length v out gnd LTC4365 r2 2370k r1 40.2k r3 100k c out 100f + c in 1000f d1 optional + 9 2a/div gnd gnd 0a 20v/div 20v/div 4365 f15 250ns/div gate v out v in i in gate v out figure 14. ov fault with large v in inductance figure 15. transients during ov fault when no tranzorb (tvs) is used www.datasheet.in
LTC4365 15 4365f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637) ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.52 max 0.65 ref recommended solder p ad la yout per ipc calcula tor 1.4 min 2.62 ref 1.22 ref 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.50 bsc www.datasheet.in
LTC4365 16 4365f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0910 ? printed in usa related parts typical application v in uv ov shdn ov = 18v uv = 3.5v 4365 ta02 v out fault gate si4230 30v dual n-channel 3.5v to 18v input range v out protected from ?30v to 30v v in 12v nominal v out gnd LTC4365 510k 4.7f ceramic 2.2nf 1820k 243k 59k v in sync v c shdn v sw fb gnd boost lt1765-3.3 4.7f ceramic output 3.3v 2.5a cmdsh-3 ups120 1.5h 0.18f LTC4365 protects step down regulator from C30v to 30v v in faults part number description comments ltc4356 surge stopper overvoltage/overcurrent protection regulator wide operating range: 4v to 80v, reverse protection to C60v, adjustable output clamp voltage ltc1696 overvoltage protection controller thinsot package, 2.7v to 28v ltc1735 high efficiency synchronous step-down switching regulator output fault protection, 16-pin ssop ltc1778 no r sense ? wide input range synchronous step-down controller up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), i out up to 20a ltc2909 triple/dual inputs uv/ov negative monitor pin selectable input polarity allows negative and ov monitoring ltc2912/ltc2913 single/dual uv/ov voltage monitor ads uv and ov trip values, 1.5% threshold accuracy ltc2914 quad uv/ov monitor for positive and negative supplies ltc3727/ltc3727-1 2-phase, dual, synchronous controller 4v v in 36v, 0.8v v out 14v ltc3827/ltc3827-1 low i q , dual, synchronous controller 4v v in 36v, 0.8v v out 10v, 80a quiescent current ltc3835/ltc3835-1 low i q , synchronous step-down controller single channel ltc3827/ltc3827-1 lt3845 low i q , synchronous step-down controller 4v v in 60v, 1.23v v out 36v, 120a quiescent current lt3850 dual, 550khz, 2-phase synchronous step-down controller dual 180 phased controllers, v in 4v to 24v, 97% duty cycle, 4mm 4mm qfn-28, ssop-28 packages lt4256 positive 48v hot swap controller with open-circuit detect foldback current limiting, open-circuit and overcurrent fault output, up to 80v supply ltc4260 positive high voltage hot swap controller with adc and i 2 c wide operating range 8.5v to 80v ltc4352 ideal mosfet oring diode external n-channel mosfets replace oring diodes, 0v to 18v ltc4354 negative voltage diode-or controller controls two n-channel mosfets, 1s turn-off, 80v operation ltc4355 positive voltage diode-or controller controls two n-channel mosfets, 0.5s turn-off, 80v operation www.datasheet.in

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